Integrated circuits (IC) are increasing in complexity. The number of devices incorporated within a single IC is greatly increasing and causing the size and complexity of individual ICs to increase. As a result of increased component density and improved fabrication technology is the realization of system on chip (SoC) applications. FIG. 1 depicts such an IC or SoC 10 that may include many logic and memory functions within the SoC. For example, core 12, as further described in FIG. 2, may include a CPU core 20, DSP core 22, DSP book 24, memory 26, control circuitry 28 and analog/mixed signal circuitry 30. These are just examples of the types of systems or components that may be integrated into a signal chip.
Complexities are associated with the realization of SoC designs. Incorporating diverse components previously contained within printed circuit board (PCB) involves confronting many design challenges. The discrete components may be designed for different entities using different tools. Other difficulties lie in fabrication. In general, fabrication processes of memory may differ significantly from those associated with logic circuits. For example, speed may be the priority associated with a logic circuit while current leakage of the stored charge is of priority for memory circuits. Therefore, multi-level interconnect schemes using five to six levels of metal are essential for logic ICs in order to offer improved speed, while memory circuits may need only two to three levels.
In order for the IC to be useful, the IC must have physical connections to the outside world. Two extremes in IC development support different types of interfaces to external devices. Low cost packaging which supports low pin count is achieved with traditional wire bond attached chips. High cost packaging may support high pin count in the case of flip chips.
With wire bond attached chips such as IC 10 as illustrated in FIG. 1, pads 14, I/O cells 18 are placed at the edge of die 16. I/O cells 18 may be decoupled from core circuitry 12 by isolation structures. This ensures that electrical noise is not coupled into core 12. Additional circuitry for latch up and electrostatic discharge (ESD) protection may be placed within cells that form a ring around the dye which is called the I/O pad ring. Bond wire pads 14 are placed at the edge of the die outside I/O circuitry. Thus, this geometry further increases the size of die 16, and may [insert complete]
Traditional ICs fall into two general categories, core-limited and I/O or pad limited. A core-limited chip is one where the size of the chip is dependent on the amount of logic contained therein. The perimeter of the chip is more than sufficient to support the I/O, clock, power, and ground bonding pads surrounding the core. A pad-limited IC's size is dictated by the bonding pads on the die's perimeter, wherein pads 14 are as close as possible, consistent with the IC's design rules. Thus pad limited IC's often contain wasted open space within die.
Advances in device density within the core have made it possible to reduce core size of IC devices. However, reduced I/O pad pitch (the pitch is typically defined as the repeat distance between adjacent I/O pads 14) has been hard to achieve because of packaging limitations. Therefore, as a result, IC designs that are I/O intensive tend to have a die size significantly greater than that of the core. This leads to poor utilization of the silicon area and a reduced number of die per wafer.